Magnetic random access memory devices including magnets adjacent magnetic tunnel junction structures and related methods

ABSTRACT

A magnetic random access memory device may include a memory cell access transistor on a substrate, a bit line spaced apart from the substrate, and a magnetic tunnel junction structure electrically coupled between the bit line and the memory cell access transistor. At least one magnet may be positioned adjacent a sidewall of the magnetic tunnel junction structure and may be configured to provide a magnetic field through the magnetic tunnel junction structure. Related methods of operating magnetic random access memory devices are also discussed.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No.10-2004-0084584, filed Oct. 21, 2004, the disclosure of which is herebyincorporated by reference herein in its entirety.

FIELD OF THE INVENTION

The present invention relates to semiconductor memory devices and, moreparticularly, to magnetic random access memory devices and methods.

BACKGROUND OF THE INVENTION

Magnetic random access memory (MRAM) devices are non-volatile memorydevices, in which information may be stored based on a magnetoresistiveeffect of an electrically conductive material therein. In particular,the resistance of the electrically conductive material may be changeddepending on an applied magnetic field. MRAM devices may include aplurality of MRAM cells made up of magnetic tunnel junction structures(MTJs) on a single transistor.

The MTJ structure may include multiple thin layers, such as a thininsulating layer sandwiched between two thin ferromagnetic layers.Electrons may tunnel through the thin insulating layer when an externalelectrical signal is applied. The upper thin magnetic layer is called afree layer, and the lower thin magnetic layer is called a pinned layer.

When the magnetization directions of the free layer and the pinned layerare parallel to each other, a tunneling current flowing through the MTJmay be increased. In other words, the tunneling resistance of thejunction may be reduced. In contrast, when the magnetization directionsof the free layer and the pinned layer are antiparallel to each other,the tunneling current flowing through the MTJ may be decreased, i.e.,the tunneling resistance of the junction may be increased.

MRAM devices may employ magnetic charges to store information, incontrast to conventional memory devices which may employ electricalcharges. In other words, digital data (represented by “0” and “1”) maybe stored based on a low resistance state (in which the magnetizationdirections of the two thin magnetic layers are parallel to each other)and a high resistance state (in which the magnetization directions ofthe two thin magnetic layers are antiparallel to each other).

An anti-ferromagnetic layer, referred to as a pinning layer, may beadded to the pinned layer. The pinning layer may serve to fix themagnetization direction of the pinned layer. In particular, the pinnedlayer may be directly on the pinning layer and may have a relativelylarge switching field. The magnetization direction of the pinned layermay be fixed in a constant direction when an applied magnetic field isless than the switching field. Thus, the digital data stored in the MRAMcell (i.e., “0” or “1”) may be determined based on the magnetizationdirection of the free layer. The magnetization direction of the freelayer may be changed by the application of a magnetic field. Moreparticularly, to change the magnetization direction of the free layer toa desired direction, conductive interconnections (such as a bit lineand/or a digit line) may be formed orthogonal to each other above andbelow the MTJ. Then as current flows through each conductiveinterconnection, a magnetic field may be induced by the current.

MTJs may be provided having a rectangular or elliptical shape when seenin a plan view, as magnetic spins in the free layer may be in a morestable state when the magnetic spins are parallel to the longitudinaldirection of the free layer.

An MRAM device may include a plurality of MTJs, which may havenon-uniform switching characteristics based on their respectivefabrication processes. As such, the external magnetic fields for storingdesired data in the respective MTJs may be different from one another.Accordingly, the greater the number of MTJs, having non-uniformswitching characteristics, the lower the write margin for the MRAMdevice. In particular, when the MTJs are scaled down to provide higherintegration density, the write margin may be significantly reduced. Inother words, during a write operation for storing desired data in aselected one of the MTJs, undesired data may be written to othernon-selected MTJs that share the bit line and/or the digit lineelectrically connected to the selected MTJ. As such, with conventionalwriting methods, write disturbance may occur, and undesired data may bestored in non-selected MTJs during a write operation for storing data ina selected MTJ.

Furthermore, a conventional MRAM cell may have a digit line disposedaround the MTJ. Typically, the digit line may be positioned below theMTJ, and the MTJ may have a lower electrode overlapping the digit line.The lower electrode may be electrically connected to a drain region ofan access transistor below the digit line. Thus, the lower electrode mayextend along a horizontal direction to connect to a contact plug to beformed on the drain region. As a result, an amount by which the planararea of the MRAM cell can be reduced may be limited due to presence ofthe digit line.

In recent years, MRAM devices have been introduced which employ a spininjection mechanism to address problems related to write disturbanceand/or integration density. For example, MRAM devices employing a spininjection mechanism are disclosed in U.S. Pat. No. 6,130,814 to Sunentitled “Current-induced magnetic switching device and memory includingthe same”. Other MRAM devices employing a spin injection mechanism aredisclosed in U.S. Pat. No. 6,603,677 to Redon et al. entitled“Three-Layered Stacked Magnetic Spin Polarization Device with Memory”.The disclosures of U.S. Pat. Nos. 6,130,814 and 6,603,677 are herebyincorporated by reference herein in their entirety.

However, in order to switch the MRAM cell using a spin injectionmechanism, a write current density greater than a critical currentdensity may be required. As such, the access transistor may requiresufficient drive current capability to provide a write current that isgreater than the critical current density. In other words, for MRAMcells employing spin injection mechanisms, scale-down may be limited bycurrent requirements of the access transistors.

SUMMARY OF THE INVENTION

Some embodiments of the present invention may provide methods ofoperating an MRAM device capable of reducing a write current used tosuccessfully switch the selected MRAM cell between a high and a lowresistance state.

In some embodiments of the present invention, methods may be provided toprogram and read a magnetic random access memory device with a magnetictunnel junction (MTJ). The programming methods may include disposing atleast one pair of magnets at both sides of the MTJ to apply a hard axismagnetic field to the MTJ, and forcing a write current to the MTJ. Thewrite current may be a positive write current flowing from a free layerof the MTJ to a pinned layer of the MTJ or a negative write currentflowing from the pinned layer of the MTJ to the free layer of the MTJ.As a result, magnetic polarizations in the free layer may be orientedparallel to or antiparallel to magnetic polarizations in the pinnedlayer.

Forcing the write current may include turning on a switching deviceelectrically connected to one terminal of the MTJ, and applying awriting signal to a bit line electrically connected to the otherterminal of the MTJ. In this case, the positive write current or thenegative write current may flow through both the MTJ and the switchingdevice connected to the MTJ.

The magnet may be a permanent magnet or an electromagnet in addition,the magnet may be disposed in a hard axis direction of the MTJ.

The free layer and/or the pinned layer may be a syntheticanti-ferromagnetic (SAF) layer including a bottom ferromagnetic layer, atop ferromagnetic layer, and an anti-ferromagnetic coupling spacer layerpositioned between the bottom and top ferromagnetic layers.

Reading the MRAM device may include applying a read voltage to bothterminals of the MTJ to sense an amount of read current flowing throughthe MTJ. The read current may be smaller than the write current.

In other embodiments of the present invention, methods may be providedto program and read a magnetic random access memory device with amagnetic tunnel junction (MTJ) and a bit line. The programming methodsmay include disposing a magnetic layer covering sidewalls and a topsurface of the bit line to apply a hard axis magnetic field to the MTJ,and forcing a write current to the MTJ. The write current may be apositive write current flowing from a free layer of the MTJ to a pinnedlayer of the MTJ or a negative write current flowing from the pinnedlayer of the MTJ to the free layer of the MTJ. As a result, magneticpolarizations in the free layer may be oriented parallel to orantiparallel to magnetic polarizations in the pinned layer.

The magnetic layer may be a permanent magnet or an electromagnet.

The bit line may be disposed parallel to an easy axis of the MTJ ordisposed to have a plane intersection angle less than 90° from the easyaxis.

In yet other embodiments of the present invention, methods may beprovided to program and read a magnetic random access memory device witha magnetic tunnel junction (MTJ) and a bit line. The programming methodsmay include disposing at least one pair of magnets at both sides of theMTJ, disposing a magnetic layer covering sidewalls and a top surface ofthe bit line to apply a hard axis magnetic field to the MTJ; and forcinga write current to the MTJ. The write current may be a positive writecurrent flowing from a free layer of the MTJ to a pinned layer of theMTJ or a negative write current flowing from the pinned layer of the MTJto the free layer of the MTJ. As a result, magnetic polarizations in thefree layer may be oriented parallel to or antiparallel to magneticpolarizations in the pinned layer.

In some embodiments of the present invention, a magnetic random accessmemory device may include a memory cell access transistor on asubstrate, a bit line spaced apart from the substrate, and a magnetictunnel junction structure electrically coupled between the bit line andthe memory cell access transistor. At least one magnet adjacent asidewall of the magnetic tunnel junction structure may be configured toprovide a magnetic field through the magnetic tunnel junction structure.For example, the at least one magnet may be configured to provide themagnetic field along a hard magnetization axis of the magnetic tunneljunction structure.

In other embodiments, a distance between the bit line and the substratemay be greater than a distance between the at least one magnet and thesubstrate. The at least one magnet may include a pair of magnetsadjacent opposing sidewalls of the magnetic tunnel junction structure atopposite sides of the bit line.

In some embodiments, the magnetic random access memory device mayfurther include a controller coupled to the memory cell accesstransistor, the bit line, and the magnetic field conductive line. Thecontroller may be configured to provide a writing current through thebit line, through the magnetic tunnel junction structure and through thememory cell access transistor while the at least one magnet provides themagnetic field through the magnetic tunnel junction structure. Forexample, the controller may be configured to provide a first writingcurrent in a first direction to reduce a resistance of the magnetictunnel junction structure. The controller may also be configured toprovide a second write current in a second direction opposite the firstdirection to increase the resistance of the magnetic tunnel junctionstructure.

In addition, in some embodiments, the controller may be configured toprovide a read current that is less than the writing current through thebit line, through the magnetic tunnel junction structure and through thememory cell access transistor. The controller may be configured todetermine a program status of the magnetic tunnel junction structurebased on the read current.

In other embodiments, the magnetic tunnel junction structure may includea pinned layer, a free layer, and an insulating layer therebetween. Theat least one magnet may be configured to provide the magnetic fieldthrough the free layer of the magnetic tunnel junction structure.

In some embodiments, the free layer and the pinned layer may be formedof a same material. In other embodiments, at least one of the pinnedlayer and/or the free layer may be a synthetic anti-ferromagnetic layer.

In some embodiments, the at least one magnet may be at least onepermanent magnet. In other embodiments, the at least one magnet may beat least one electromagnet.

In some embodiments, the at least one magnet may be a first magnetconfigured to provide a first magnetic field through the magnetic tunneljunction structure. A second magnet on opposing sidewalls of the bitline and a surface therebetween opposite the magnetic tunnel junctionstructure may be configured to provide a second magnetic field throughthe magnetic tunnel junction structure along a same direction as thefirst magnetic field.

According to other embodiments of the present invention, a magneticrandom access memory device may include a memory cell access transistoron a substrate, a bit line spaced apart from the substrate, and amagnetic tunnel junction structure electrically coupled between the bitline and the memory cell access transistor.

A magnet on opposing sidewalls of the bit line and a surfacetherebetween opposite the magnetic tunnel junction structure may beconfigured to provide a magnetic field through the magnetic tunneljunction structure. For example, the magnet may be configured to providethe magnetic field along a hard magnetization axis of the magnetictunnel junction structure.

In some embodiments, the magnetic random access memory device mayinclude a controller coupled to the memory cell access transistor, thebit line, and the magnetic field conductive line. The controller may beconfigured to provide a writing current through the bit line, throughthe magnetic tunnel junction structure and through the memory cellaccess transistor while the magnet provides the magnetic field throughthe magnetic tunnel junction structure. For example, the controller maybe configured to provide a first writing current in a first direction toreduce a resistance of the magnetic tunnel junction structure. Also, thecontroller may be configured to provide a second write current in asecond direction opposite the first direction to increase the resistanceof the magnetic tunnel junction structure.

In other embodiments, the controller may be configured to provide a readcurrent that is less than the writing current through the bit line,through the magnetic tunnel junction structure and through the memorycell access transistor The controller may be configured to determine aprogram status of the magnetic tunnel junction structure based on theread current.

In some embodiments, the magnet may be a permanent magnet. In otherembodiments, the magnet may be an electromagnet.

In some embodiments, the magnet may be a first magnet configured toprovide a first magnetic field through the magnetic tunnel junctionstructure. A pair of second magnets adjacent opposing sidewalls of themagnetic tunnel junction structure may be configured to provide a secondmagnetic field through the magnetic tunnel junction structure along asame direction as the first magnetic field.

According to further embodiments of the present invention, a method ofoperating a magnetic random access memory device is provided. Themagnetic random access memory device may include a memory cell having amagnetic tunnel junction structure connected between a bit line and amemory cell access transistor on a substrate, and at least one magnetadjacent a sidewall of the magnetic tunnel junction structure. Amagnetic field may be provided through the magnetic tunnel junctionstructure using the at least one magnet. A writing current may beprovided through the bit line, through the magnetic tunnel junctionstructure and through the memory cell access transistor while providingthe magnetic field.

In some embodiments, the at least one magnet may include a pair ofmagnets adjacent opposing sidewalls of the magnetic tunnel junctionstructure. The magnetic field may be provided along a hard magnetizationaxis of the magnetic tunnel junction structure.

In other embodiments, a first writing current may be provided in a firstdirection to reduce a resistance of the magnetic tunnel junctionstructure. Also, a second writing current may be provided in a seconddirection opposite the first direction to increase the resistance of themagnetic tunnel junction structure.

In some embodiments, a read current that is less than the writingcurrent may be provided through the bit line, through the magnetictunnel junction structure and through the memory cell access transistor.A program status of the magnetic tunnel junction structure may bedetermined based on the read current.

In other embodiments, the at least one magnet may be at least oneelectromagnet. A current may be provided through the electromagnet togenerate the magnetic field.

In some embodiments, the at least one magnet may be a first magnet, andthe magnetic field may be a first magnetic field. A second magneticfield may be provided through the magnetic tunnel junction structure ina same direction as the first magnetic field using a second magnet onopposing sidewalls of the bit line and a surface therebetween oppositethe magnetic tunnel junction structure. The writing current may beprovided while providing the second magnetic field.

According to still further embodiments of the present invention, amethod of operating a magnetic random access memory device is provided.The magnetic random access memory device may include a memory cellhaving a magnetic tunnel junction structure connected between a bit lineand a memory cell access transistor on a substrate, and a magnet onopposing sidewalls of the bit line and a surface therebetween oppositethe magnetic tunnel junction structure. A magnetic field may be providedthrough the magnetic tunnel junction structure using the magnet. Awriting current may be provided through the bit line, through themagnetic tunnel junction structure and through the memory cell accesstransistor while providing the magnetic field.

In some embodiments, the magnetic field may be provided along a hardmagnetization axis of the magnetic tunnel junction structure.

In other embodiments, the magnet may be an electromagnet. A current maybe provided through the electromagnet to generate the magnetic field.

In some embodiments, the magnet may be a first magnet and the magneticfield may be a first magnetic field. A second magnetic field may beprovided through the magnetic tunnel junction structure in a samedirection as the first magnetic field using a pair of second magnetsadjacent opposing sidewalls of the magnetic tunnel junction structure atopposite sides of the bitline. The writing current may be provided whileproviding the second magnetic field.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view of an MRAM device in accordance with someembodiments of the present invention.

FIG. 2 is a cross-sectional view taken along line I-I′ of FIG. 1.

FIG. 3 is a cross-sectional view taken along line II-II′ of FIG. 1.

FIG. 4 is a perspective view of an MRAM device in accordance withfurther embodiments of the present invention.

FIG. 5 is a cross-sectional view taken along line III-III′ of FIG. 4.

FIG. 6 is a perspective view of a portion of an MRAM device inaccordance with still further embodiments of the present invention.

FIG. 7 is a cross-sectional view taken along line V-V′ of FIG. 6.

FIG. 8 is a perspective view of an MRAM device including a controllerconnected thereto in accordance with some embodiments of the presentinvention.

FIG. 9 is a perspective view of an MRAM device including a controllerconnected thereto in accordance with further embodiments of the presentinvention.

FIG. 10 is a perspective view of an MRAM device including a controllerconnected thereto in accordance with still further embodiments of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which embodiments of theinvention are shown. However, this invention should not be construed aslimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure will be thorough and complete, andwill fully convey the scope of the invention to those skilled in theart. In the drawings, the thickness of layers and regions areexaggerated for clarity. Like numbers refer to like elements throughoutthe specification.

It will be understood that when an element such as a layer, region orsubstrate is referred to as being “on” or extending “onto” anotherelement, it can be directly on or extend directly onto the other elementor intervening elements may also be present. In contrast, when anelement is referred to as being “directly on” or extending “directlyonto” another element, there are no intervening elements present. Itwill also be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present.

It will also be understood that, although the terms first, second, etc.may be used herein to describe various elements, these elements shouldnot be limited by these terms. These terms are only used to distinguishone element from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present invention.

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or“top,” may be used herein to describe one element's relationship toanother elements as illustrated in the Figures. It will be understoodthat relative terms are intended to encompass different orientations ofthe device in addition to the orientation depicted in the Figures. Forexample, if the device in one of the figures is turned over, elementsdescribed as being on the “lower” side of other elements would then beoriented on “upper” sides of the other elements. The exemplary term“lower”, can, therefore, encompass both an orientation of “lower” and“upper,” depending of the particular orientation of the figure.Similarly, if the device in one of the figures is turned over, elementsdescribed as “below” or “beneath” other elements would then be oriented“above” the other elements. The exemplary terms “below” or “beneath”can, therefore, encompass both an orientation of above and below.

The terminology used in the description of the invention herein is forthe purpose of describing particular embodiments only and is notintended to be limiting of the invention. As used in the description ofthe invention and the appended claims, the singular forms “a”, “an” and“the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise. It will also be understood that theterm “and/or” as used herein refers to and encompasses any and allpossible combinations of one or more of the associated listed items.

Embodiments of the invention are described herein with reference tocross-section illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures) of the invention. Assuch, variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, embodiments of the invention should not be construed aslimited to the particular shapes of regions illustrated herein but areto include deviations in shapes that result, for example, frommanufacturing. For example, an implanted region illustrated as arectangle will, typically, have rounded or curved features and/or agradient of implant concentration at its edges rather than a binarychange from implanted to non-implanted region. Likewise, a buried regionformed by implantation may result in some implantation in the regionbetween the buried region and the surface through which the implantationtakes place. Thus, the regions illustrated in the figures are schematicin nature and their shapes are not intended to illustrate the actualshape of a region of a device and are not intended to limit the scope ofthe invention.

Unless otherwise defined, all terms used in disclosing embodiments ofthe invention, including technical and scientific terms, have the samemeaning as commonly understood by one of ordinary skill in the art towhich this invention belongs, and are not necessarily limited to thespecific definitions known at the time of the present invention beingdescribed. Accordingly, these terms can include equivalent terms thatare created after such time. All publications, patent applications,patents, and other references mentioned herein are incorporated byreference in their entirety.

FIG. 1 is a perspective view of an MRAM device in accordance with someembodiments of the present invention. FIG. 2 is a cross-sectional viewtaken along line I-I′ of FIG. 1, and FIG. 3 is a cross-sectional viewtaken along line II-II′ of FIG. 1.

Referring now to FIGS. 1, 2, and 3, an MRAM device according to someembodiments of the present invention includes an isolation layer 3, adrain region 7 d, a source region 7 s, and a channel region in apredetermined region of an integrated circuit (IC) substrate 1. Thechannel region is positioned between the drain region 7 d and the sourceregion 7 s, and an insulated gate electrode 5 is positioned above thechannel region. The gate electrode 5 may serve as a word line.Consequently, the drain region 7 d, the source region 7 s, and the gateelectrode 5 define a switching device, for example, an access transistorTA, on the substrate 1.

A first lower interlayer insulating layer 9 is formed on the substrate 1including the access transistor TA. The source region 7 s may be exposedby a source contact hole extending through the first lower interlayerinsulating layer 9, and the source contact hole may be filled by asource contact plug 11. A source line 13 is formed on the source contactplug 11. As such, the source line 13 is electrically connected to thesource region 7 s via the source contact plug 11.

A first upper interlayer insulating layer 15 is formed on the substrateI including the source line 13. The first lower interlayer insulatinglayer 9 and the first upper interlayer insulating layer 15 form a firstinterlayer insulating layer 16. The drain region 7 d may be exposed by adrain contact hole extending through the first interlayer insulatinglayer 16. The drain contact hole may be filled by a drain contact plug17. As such, the drain contact plug 17 is electrically connected to thedrain region 7 d.

A magnetic resistor 45 is formed on the first interlayer insulatinglayer 16 and on the drain contact plug 17. The magnetic resistor 45includes a lower electrode 19, an upper electrode 43, and a magnetictunnel junction structure (MTJ) 41 positioned therebetween. The MTJ 41includes a pinned layer 29, a free layer 39, and a tunneling insulatinglayer 31 positioned between the pinned layer 29 and the free layer 39.Furthermore, the MTJ 41 may include a pinning layer 21 contacting thepinned layer 29. Respective layers 19, 21, 29, 31, 39, and 43 of themagnetic resistor 45 may be stacked in various orders. For example, thelower electrode 19 may be in contact with the drain contact plug 17, andthe pinning layer 21, the pinned layer 29, the tunneling insulatinglayer 31 and the free layer 39 may be stacked on the lower electrode 19in the above order.

The free layer 39 may be a single layer of ferromagnetic material, or asynthetic anti-ferromagnetic (SAF) layer having a lower ferromagneticlayer 33, an anti-ferromagnetic coupling spacer layer 35, and an upperferromagnetic layer 37 which are sequentially stacked as shown in FIGS.2 and 3.

In addition, the pinned layer 29 may be a single layer of ferromagneticmaterial, or a synthetic anti-ferromagnetic (SAF) layer having a lowerferromagnetic layer 23, an anti-ferromagnetic coupling spacer layer 25,and an upper ferromagnetic layer 27 which are sequentially stacked asshown in FIGS. 2 and 3.

A second interlayer insulating layer 47 is formed on the firstinterlayer insulating layer 16 and on the magnetic resistor 45. A bitline 49 is formed on the second interlayer insulating layer 47. The bitline 49 is electrically connected to the magnetic resistor 45 via theupper electrode 43.

The MTJ 41 may have a rectangular or an elliptical shape (including alength and a width that is smaller than the length) when seen in a planview. As such, the MTJ 41 may have an easy magnetization axis along thelength direction (parallel to the substrate) and a hard magnetizationaxis along the width direction (parallel to the substrate andperpendicular to the length direction).

At least one pair of magnets 52 may be positioned at opposing sidewallsof the MTJ 41. More particularly, one of the magnets 52 may bepositioned at one side of the hard axis, and the other may be positionedat the other side of the hard axis. The magnets 52 may be spaced apartfrom the MTJ 41 by portions of the second interlayer 47. The magnets 52may be permanent magnets and/or electromagnets.

Methods for writing and/or programming an MRAM device according to someembodiments of the present invention will now be described withreference to FIGS. 1, 2, and 3.

Referring again to FIGS. 1, 2, and 3, a word line signal is applied tothe word line (i.e., the gate electrode 5) of the access transistor TAand a bit line write signal is applied to the bit line 49. The word linesignal may be a voltage pulse signal having a voltage higher than athreshold voltage of the access transistor TA, and may be applied for apredetermined time. The access transistor TA connected to the word line5 is turned on while the word line signal is applied. The bit line writesignal may be a current pulse signal providing current to the bit linewhen the word line signal is applied. As a result, an MRAM cellconnected to the word line and the bit line may be selected, and awriting current may flow through the MTJ of the selected MRAM cell andthe access transistor TA serially connected to the cell. For example,when the word line signal and the bit line write signal are applied tothe word line 5 and the bit line 49, respectively, the MRAM cellconnected to the word line 5 and the bit line 49 may be selected, andthe write current may flow through the MTJ 41 of the selected MRAM cell.

The write current may be a positive write current +IW which flows fromthe free layer 39 to the pinned layer 29 in the selected MTJ 41, or anegative write current −IW which flows from the pinned layer 29 to thefree layer 39 in the selected MTJ 41. As used herein, “current” refersto the flow of electrical charges from a higher potential to a lowerpotential. As such, the positive write current +IW flows in a directionof the negative Z-axis, as shown in FIGS. 2 and 3, and the negativewrite current −IW flows in a direction of the positive Z-axis, as alsoshown in FIGS. 2 and 3. More particularly, electrons flow in thepositive Z-axis direction when the positive write current +IW isapplied, and electrons flow in the negative Z-axis direction when thenegative write current −IW is applied.

When the source line 13 is grounded during a writing/programmingoperation, the positive write current +IW may be generated by applying apositive program voltage to the selected bit line. Similarly, when thesource line 13 is grounded during the writing/programming operation, thenegative write current −IW may be generated by applying a negativeprogram voltage to the selected bit line.

When the positive write current +IW flows through the selected MTJ 41, amajority of the electrons passing through the pinned layer 29 may bechanged to have spins in the same magnetization direction as the fixedmagnetic polarizations and/or moments in the pinned layer 29. Forexample, when a majority of the magnetic polarizations/moments haveup-spins in the pinned layer 29, a majority of the electrons passingthrough the pinned layer 29 may be changed to have up-spins. Inparticular, when the pinned layer 29 is a SAF layer as described above,a majority of the electrons are changed to have spins in the samemagnetization direction as that of the upper ferromagnetic layer 27 ofthe SAF pinned layer.

The up-spin electrons may pass through the tunneling insulating layer 31to reach the free layer 39. The number of up-spin electrons reaching thefree layer 39 may be proportional to the current density of the positivewrite current +IW. As a result, when the positive write current densityis increased, a majority of the magnetic polarizations/moments in thefree layer 39 may be parallel to the fixed magneticpolarizations/moments of the pinned layer 29 (regardless of the initialmagnetization direction), due to the up-spin electrons injected into thefree layer 39. For example, when the free layer 39 is a SAF layer asdescribed above, application of the positive write current +IW orientsmagnetic polarizations/moments in the lower ferromagnetic layer 33 ofthe SAF free layer parallel to the fixed magnetic polarizations/momentsin the pinned layer 29. In addition, when both the pinned layer 29 andthe free layer 39 are SAF layers as shown in FIGS. 2 and 3, applicationof the positive write current +IW orients magnetic polarizations/momentsin the lower ferromagnetic layer 33 of the SAF free layer parallel tothe fixed magnetic polarizations/moments in the upper ferromagneticlayer 27 of the SAF pinned layer 29. Accordingly, when the positivewrite current density is greater than a critical current density, theselected MTJ 41 may have a relatively low resistance value.

Similarly, when the negative write current =IW flows through theselected MTJ 411 electrons may be injected into the free layer 39. Theelectrons may include up-spin electrons and down-spin electrons. When amajority of the fixed magnetic polarizations/moments in the pinned layer29 have up-spins, only the up-spin electrons injected into the freelayer 39 may pass through the selected tunneling insulating layer 31 toreach the pinned layer 29. As such, the down-spin electrons mayaccumulate in the free layer 39. The number of up-spin electrons anddown-spin electrons may be proportional to the current density of thenegative write current −IW. Accordingly, when the negative write currentdensity is increased, a majority of the magnetic polarizations/momentsof the free layer 39 may be antiparallel to the magnetization directionof the pinned layer 29 (regardless of the initial magnetizationdirection). Thus, when the negative write current density is greaterthan the critical current density, the selected MTJ 41 may have arelatively high resistance value.

In order to change the resistance of the selected MRAM cell using thespin injection mechanism as described above, a write current densitygreater than the critical current density may be required. Accordingly,an access transistor TA having drive current capability sufficient totransmit a write current greater than the critical current density maybe required. As such, when the selected MRAM cell is programmed using aspin injection mechanism requiring a higher write current density, itmay be difficult to scale-down the access transistor TA. In other words,the access transistor TA may be a limiting factor in improving theintegration density of the MRAM device. Accordingly, in order to providewriting/programming operations capable of reducing the write currentdensity used to successfully change the resistance of the selected MRAMcell, some embodiments of the present invention may employ a magnet 52positioned at one or more sidewalls of the MTJ 41 to generate a hardaxis magnetic field Hh through the MTJ 41.

Writing/programming operations according to some embodiments of thepresent invention may include applying the word line signal and the bitline write signal, and applying the hard axis magnetic field Hh via themagnet(s) 52 positioned adjacent sidewalls of the MTJ 41. The hard axismagnetic field Hh may be a magnetic field that is parallel to the widthdirection of the MTJ 41, i.e., the hard axis direction of the MTJ 41.

More particularly, the hard axis magnetic field Hh may be generated byat least a pair of magnets 52 which are adjacent to opposing sidewallsof the MTJ 41, as shown in FIGS. 1 and 3. The hard axis magnetic fieldHh is parallel to the hard magnetization axis of the MTJ 41, (i.e., theX-axis or width direction). When the write current is applied incombination with the hard axis magnetic field Hh, the magnetization ofthe MTJ 41 may be more easily switched due to the presence of the hardaxis magnetic field Hh. For example, when the positive write current +IWis provided in the presence of the hard axis magnetic field Hh, magneticpolarizations/moments in the free layer 39 may be arranged parallel tomagnetic polarizations/moments in the pinned layer 29 more easily, evenwhen the positive write current +IW is relatively low. Similarly, whenthe negative write current −IW is provided in the presence of the hardaxis magnetic field Hh, magnetic polarizations/moments in the free layer39 may be arranged antiparallel to magnetic polarizations/moments in thepinned layer 29 more easily, even when the negative write current −IW isrelatively low. As such, the hard axis magnetic field Hh may reduce awrite current required to successfully switch the magnetization of thefree layer 39 of the MTJ 41. In other words, application of the hardaxis magnetic field Hh may lower the critical current density.

Still referring to FIGS. 1, 2, and 3, methods of reading the data storedin the MRAM cell may include applying a read voltage to both terminalsof the MTJ 41 of the MRAM cell. For example, in order to read the datastored in the MRAM cell, a word line voltage may be applied to the wordline to turn on the access transistor TA connected to the word line, anda ground voltage and a read voltage may be applied to the source line 13and the bit line 49, respectively. As a result, the read current mayflow through the MTJ 41 of the MRAM cell, and it may be determinedwhether the data stored in MRAM cell has a logic “0” or logic “1” valueaccording to the amount of the read current. The read voltage may besufficiently low in order to provide a read current that is less than aminimum write current.

FIG. 4 is a perspective view of a MTJ in a MRAM device in accordancewith further embodiments of the present invention. FIG. 5 is across-sectional view taken along line III-III′ of FIG. 4.

Referring to FIGS. 4 and 5, a MRAM device according to furtherembodiments of the present invention may include structures similar tothose described above with reference to FIGS. 1 to 3, including theintegrated circuit substrate 1, the first interlayer insulating layer 16and the structures therebetween. In addition, the drain contact plug 17extending through the first interlayer insulating layer 16 has a similarstructure to that described above with reference to FIGS. 1 to 3.

A magnetic resistor 45 is formed on the first interlayer insulatinglayer 16 and on the drain contact plug 17. The magnetic resistor 45includes a lower electrode 19, an upper electrode 43, and an MTJ 41positioned therebetween. The MTJ 41 includes a pinned layer 29, a freelayer 39, and a tunneling insulating layer 31 positioned therebetween.Furthermore, the MTJ 41 may include a pinning layer 21 contacting thepinned layer 29. Respective layers 19, 21, 29, 31, 39, and 43 of themagnetic resistor 45 may be stacked in various orders. For example, thelower electrode 19 may be in contact with the drain contact plug 17, andthe pinning layer 21, the pinned layer 29, the tunneling insulatinglayer 31, and the free layer 39 may be stacked on the lower electrode 19in the above order.

The free layer 39 may be a single layer of ferromagnetic material, or asynthetic anti-ferromagnetic (SAF) layer having a lower ferromagneticlayer 33, an anti-ferromagnetic coupling spacer layer 35, and an upperferromagnetic layer 37 which are sequentially stacked as shown in FIGS.2 and 5.

In addition, the pinned layer 29 may be a single layer of ferromagneticmaterial, or a synthetic anti-ferromagnetic (SAF) layer having a lowerferromagnetic layer 23, an anti-ferromagnetic coupling spacer layer 25,and an upper ferromagnetic layer 27 which are sequentially stacked, asshown in FIGS. 2 and 5.

A second interlayer insulating layer 47 is formed on the firstinterlayer insulating layer 16 and on the magnetic resistor 45. A bitline 49 is formed on the second interlayer insulating layer 47. The bitline 49 is electrically connected to the magnetic resistor 45 via theupper electrode 43.

The MTJ 41 may have a rectangular or elliptical shape (including alength and a width that is smaller than the length) when seen in a planview. As such the MTJ 41 may have an easy magnetization axis in thelength direction and a hard magnetization axis in the width direction,where the length and the width directions may be perpendicular to eachother.

A magnetic layer 59 is formed on opposing sidewalls and an upper surfacetherebetween of the bit line 49. The magnetic layer 59 may be apermanent magnet and/or an electromagnet. The magnetic layer 59 maydefine a structure covering opposing sidewalls and a surfacetherebetween (such as an upper surface) of the bit line 49.Alternatively, the magnetic layer 59 may cover only portions of thesidewalls and the upper surface of the bit line 49. In addition, themagnetic layer 59 may include a plurality of magnetic layers coveringportions of the sidewalls and/or the upper surface of the bit line 49.In such a case, the bit line 49 may be positioned parallel to the easymagnetization axis or at an intersection angle of less than 90° from theeasy magnetization axis.

Writing/programming methods according to further embodiments of thepresent invention will now be described with reference to FIGS. 4 and 5.

Referring again to FIGS. 4 and 5, a word line signal is applied to theword line (i.e., the gate electrode 5) of the access transistor TA and abit line write signal is applied to the bit line 49. The word linesignal may be a voltage pulse signal having a voltage higher than athreshold voltage of the access transistor TA, and may be applied for apredetermined time. In addition, the bit line write signal may be acurrent pulse signal providing current to the bit line when the wordline signal is applied. As a result, the MRAM cell connected to the wordline and the bit line may be selected, and the write current may flowthrough the MTJ 41 of the selected MRAM cell and the access transistorTA connected in series with the cell.

The write current may be a positive write current +IW which flows fromthe free layer 39 of the selected MTJ 41 to the pinned layer 29 thereof,or a negative write current −IW which flows from the pinned layer 29 tothe free layer 39.

When the source line 13 is grounded during a writing/programmingoperation, the positive write current +IW may be generated by applying apositive program voltage to the selected bit line. Similarly, when thesource line 13 is grounded during the writing/programming operation, thenegative write current −IW may be generated by applying a negativeprogram voltage to the selected bit line.

When the positive write current +IW flows through the selected MTJ 41, amajority of the electrons which pass through the selected pinned layer29 may be changed to have spins in the same magnetization direction asthe fixed magnetic polarizations/moments in the pinned layer 29.Accordingly, when the positive write current density is increased, amajority of the magnetic polarizations/moments in the free layer 39 maybe parallel to the fixed magnetic polarizations/moments in the selectedpinned layer 29, regardless of the initial magnetization direction. Forexample, when the free layer 39 is a SAF layer as described above,application of the positive write current +IW orients magneticpolarizations/moments in the lower ferromagnetic layer 33 of the SAFfree layer parallel to the fixed magnetic polarizations/moments in theselected pinned layer 29. In addition, when both the pinned layer 29 andthe free layer 39 are SAF layers, application of the positive writecurrent +IW orients magnetic polarizations in the lower ferromagneticlayer 33 of the SAF free layer parallel to fixed magneticpolarizations/moments in the upper ferromagnetic layer 27 of the SAFpinned layer 29. Accordingly, when the positive write current density isgreater than the critical current density, the selected MITJ 41 may havea relatively low resistance value.

Similarly, when the negative write current −IW flows through theselected MTJ 41, electrons may be injected into the free layer 39. Asdescribed above with reference to FIGS. 1 to 3, when the negative writecurrent density is greater than the critical current density, theselected MTJ 41 may have a relatively high resistance value.

In order to change the resistance of the selected MRAM cell using thespin injection mechanism as described above, a write current densitygreater than the critical current density may be required. Accordingly,writing/programming methods according to further embodiments of thepresent invention employ a magnetic layer 59 on the opposing sidewallsand the upper surface therebetween of the bit line 49 to provide a hardaxis magnetic field Hh capable of reducing the write current densityrequired to successfully change the resistance of the selected MRAMcell.

Writing/programming operations according to further embodiments of thepresent invention include applying the word line signal and the bit linewrite signal, and applying the hard axis magnetic field Hh via themagnetic layer 59 formed on the opposing sidewalls and the upper surfaceof the bit line 49 of the MTJ 41. The hard axis magnetic field Hh may bea magnetic field that is parallel to the width direction of the MTJ 41,i.e., the hard axis direction of the MTJ 41.

More specifically, the hard axis magnetic field Hh may be generated bythe magnetic layer 59 covering at least a portion of the opposingsidewalls and a surface therebetween of the bit line 49, as shown inFIGS. 4 and 5. The hard axis magnetic field Hh is parallel to the hardmagnetization axis of the MTJ 41, i.e., the X-axis direction. When thewrite current is applied in combination with the hard axis magneticfield Hh, the MTJ 41 may be more easily switched. For example, when thepositive write current +IW is provided in the presence of the hard axismagnetic field Hh, magnetic polarizations/moments in the free layer 39may be more easily arranged parallel to magnetic polarizations/momentsin the pinned layer 29 with the aid of the hard axis magnetic field Hh,even when the positive write current +IW is relatively low. Similarly,when the negative write current −IW is provided in the presence of thehard axis magnetic field Hh, magnetic polarizations/moments in the freelayer 39 may be more easily arranged antiparallel to magneticpolarizations/moments in the pinned layer 29 with the aid of the hardaxis magnetic field Hh, even when the negative write current −IW isrelatively low. Accordingly, the hard axis magnetic field Hh may reducea write current required to successfully switch the magnetization of thefree layer 39 of the MTJ 41. In other words, application of the hardaxis magnetic field Hh may lower the critical current density.

Methods of reading the data stored in the MRAM cell may include applyinga read voltage to both terminals of the MTJ 41 of the MRAM cell, asdescribed above with reference to FIGS. 1 to 3. For example, in order toread the data stored in the MRAM cell, a word line voltage may beapplied to the word line to turn on the access transistor TA connectedto the word line, and a ground voltage and a read voltage may be appliedto the source line 13 and the bit line 49, respectively. As a result,the read current may flow through the MTJ 41 of the MRAM cell, and itmay be determined whether the data stored in the MRAM cell has a logic“0” or logic “1” value according to the amount of the read current. Theread voltage may be sufficiently low in order to provide a read currentthat is less than a minimum write current.

FIG. 6 is a perspective view of a MTJ in a MRAM device in accordancewith still further embodiments of the present invention. FIG. 7 is across-sectional view taken along line V-V′ of FIG. 6.

Referring to FIGS. 6 and 7, a MRAM device according to still furtherembodiments of the present invention may include structures similar tothose described above with reference to FIGS. 1 to 5, including theintegrated circuit substrate 1, the first interlayer insulating layer16, and the structures therebetween. In addition, the drain contact plug17 extending through the first interlayer insulating layer 16 has asimilar structure to that described above with reference to FIGS. 1 to5.

A magnetic resistor 45 is formed on the first interlayer insulatinglayer 16 and on the drain contact plug 17. The magnetic resistor 45includes a lower electrode 19, an upper electrode 43, and an MTJ 41positioned therebetween. The MTJ 41 includes a pinned layer 29, a freelayer 39, and a tunneling insulating layer 31 positioned therebetween.Furthermore, the MTJ 41 may include a pinning layer 21 contacting thepinned layer 29. Respective layers 19, 21, 29, 31, 39, and 43 of themagnetic resistor 45 may be stacked in various orders. For example, thelower electrode 19 may be in contact with the drain contact plug 17, andthe pinning layer 21, the pinned layer 29, the tunneling insulatinglayer 31, and the free layer 39 may be stacked on the lower electrode 19in the above order.

The free layer 39 may be a single layer of ferromagnetic material, or asynthetic anti-ferromagnetic (SAF) layer having a lower ferromagneticlayer 33, an anti-ferromagnetic coupling spacer layer 35, and an upperferromagnetic layer 37 which are sequentially stacked as shown in FIGS.2 and 7.

In addition, the pinned layer 29 may be a single layer of ferromagneticmaterial, or a synthetic anti-ferromagnetic (SAF) layer having a lowerferromagnetic layer 23, an anti-ferromagnetic coupling spacer layer 25,and an upper ferromagnetic layer 27 which are sequentially stacked asshown in FIGS. 2 and 7.

A second interlayer insulating layer 47 is formed on the firstinterlayer insulating layer 16 and on the magnetic resistor 45. A bitline 49 is formed on the second interlayer insulating layer 47. The bitline 49 is electrically connected to the magnetic resistor 45 via theupper electrode 43.

The MTJ 41 may have a rectangular or elliptical shape (including alength and a width that is smaller than the length) when seen in a planview. Accordingly, the MTJ 41 may have an easy magnetization axis alongthe length direction and a hard magnetization axis along the widthdirection, where the length and the width directions may beperpendicular to each other. The bit line 49 may be parallel to thelength direction.

At least one pair of magnets 52 is positioned adjacent opposingsidewalls of the MTJ 41 at opposite sides of the bit line 49, i.e.,along the width direction. More particularly, one of the magnets 52 ispositioned at one side of the magnetization hard axis, and the other ispositioned at the other side of the hard axis, spaced apart from the MTJ41 by the second interlayer insulating layer 47. The magnets 52 may bepermanent magnets and/or electromagnets.

In addition, a magnetic layer 59 is formed on opposing sidewalls and anupper surface therebetween of the bit line 49. The magnetic layer 59 maybe a permanent magnet and/or an electromagnet. The magnetic layer 59 maydefine a structure covering the upper surface and sidewalls of the bitline 49. Alternatively, the magnetic layer 59 may cover only portions ofthe sidewalls and the upper surface of the bit line 49. In addition, themagnetic layer 59 may include a plurality of magnetic layers coveringportions of the sidewalls and/or the upper surface of the bit line 49.In such a case, the bit line 49 may be positioned parallel to the easymagnetization axis or at an intersection angle of less than 90° from theeasy magnetization axis.

Writing/programming operations according to still further embodiments ofthe present invention will now be described with reference to FIGS. 6and 7.

Referring again to FIGS. 6 and 7, a word line signal is applied to theword line (i.e., the gate electrode 5) of the access transistor TA and abit line write signal is applied to the bit line 49. The word linesignal may be a voltage pulse signal having a voltage greater than athreshold voltage of the access transistor TA, and may be applied for apredetermined time. In addition, the bit line write signal may be acurrent pulse signal providing current to the bit line when the wordline signal is applied. As a result, the MRAM cell connected to the wordline and the bit line may be selected, and the write current may flowthrough the MTJ 41 of the selected MRAM cell and the access transistorTA connected in series to the cell.

The write current may be a positive write current +IW which flows fromthe free layer 39 of the selected MTJ 41 to the pinned layer 29 thereof,or a negative write current −IW which flows from the pinned layer 29 tothe free layer 39.

When the source line 13 is grounded during a writing/programmingoperation, the positive write current +IW may be generated by applying apositive program voltage to the selected bit line. Similarly, when thesource line 13 is grounded during the writing/programming operation, thenegative write current −IW may be generated by applying a negativeprogram voltage to the selected bit line.

When the positive write current +IW flows through the selected MTJ 41, amajority of the electrons which pass through the selected pinned layer29 may be changed to have spins in the same magnetization direction asthe fixed magnetic polarizations/moments in the pinned layer 29. Whenthe positive write current density is increased, a majority of themagnetic polarizations/moments in the free layer 39 may be parallel tothe fixed magnetic polarizations/moments in the selected pinned layer 29regardless of the initial magnetization direction. For example, when thefree layer 39 is a SAF layer as described above, application of thepositive write current +IW orients the magnetic polarizations/moments inthe lower ferromagnetic layer 33 of the SAF free layer parallel to thefixed magnetic polarizations/moments in the pinned layer 29. Inaddition, when both the pinned layer 29 and the free layer 39 are SAFlayers, application of the positive write current +IW orients themagnetic polarizations/moments in the lower ferromagnetic layer 33 ofthe SAF free layer parallel to fixed magnetic polarizations/moments inthe upper ferromagnetic layer 27 of the SAF pinned layer 29. As such,when the positive write current density is greater than the criticalcurrent density, the selected MTJ 41 may have a relatively lowresistance value.

Likewise when the negative write current −IW flows through the selectedMTJ 41, electrons may be injected into the free layer 39. As describedabove with reference to FIGS. 1 to 5, when the negative write currentdensity is greater than the critical current density, the selected MTJ41 may have a relatively high resistance value.

In order to switch the magnetization (and thereby change the resistance)of the selected MRAM cell using the spin injection mechanism asdescribed above, a write current density greater than the criticalcurrent density may be required. Accordingly, writing/programmingoperations according to still further embodiments of the presentinvention employ magnets 52 adjacent the opposing sidewalls of the MTJ41 in addition to a magnetic layer 59 on the opposing sidewalls and theupper surface therebetween of the bit line 49 to generate a hard axismagnetic field Hh capable of reducing the write current density requiredto successfully switch the selected MRAM cell.

Writing/programming operations according to still further embodiments ofthe present invention, include applying the word line signal and the bitline write signal, and applying the hard axis magnetic field Hh usingboth the magnets 52 adjacent the opposing sidewalls of the MTJ 41 andthe magnetic layer 59 on the opposing sidewalls and the upper surface ofthe bit line 49 of the MTJ 41. The hard axis magnetic field Hh may be amagnetic field that is parallel to the width direction of the MTJ 41,i.e., the hard axis direction of the MTJ 41.

In greater detail, the hard axis magnetic field Hh may be generated byat least a pair of magnets 52 adjacent to and parallel to the MTJ 41 anda magnetic layer 59 covering at least a portion of the sidewalls and theupper surface of the bit line 49, as shown in FIGS. 6 and 7. The hardaxis magnetic field Hh is parallel to the hard magnetization axis of theMTJ 41, i.e., the X-axis direction. When the write current is applied incombination with the hard axis magnetic field Hh, the MTJ 41 may be moreeasily switched. For example, when the positive write current +IW isprovided in the presence of the hard axis magnetic field Hh, magneticpolarizations/moments in the free layer 39 may be more easily arrangedparallel to magnetic polarizations/moments in the pinned layer 29 withthe aid of the hard axis magnetic field Hh, even when the positive writecurrent +IW is relatively low. Similarly, when the negative writecurrent −IW is provided in the presence of the hard axis magnetic fieldHh, magnetic polarizations/moments in the free layer 39 may be moreeasily arranged antiparallel to magnetic polarizations/moments in thepinned layer 29 with the aid of the hard axis magnetic field Hh evenwhen the negative write current −IW is relatively low. Thus, the hardaxis magnetic field Hh may reduce a write current required tosuccessfully switch the MTJ 41. In other words, application of the hardaxis magnetic field Hh may lower the critical current density.

Methods of reading the data stored in the MRAM cell may include applyinga read voltage to both terminals of the MTJ 41 of the MRAM cell asdescribed above with reference to FIGS. 1 to 5. For example, in order toread the data stored in the MRAM cell, a word line voltage may beapplied to the word line to turn on the access transistor TA connectedto the word line, and a ground voltage and a read voltage may be appliedto the source line 13 and the bit line 49, respectively. As a result,the read current may flow through the MTJ 41 of the MRAM cell, and itmay be determined whether the data stored in the MRAM cell has a logic“0” or logic “1” value according to the amount of the read current. Theread voltage may be sufficiently low in order to provide a read currentthat is less than a minimum write current.

FIG. 8 is a perspective view of an MRAM device including a controllerconnected thereto in accordance with some embodiments of the presentinvention. Referring to FIG. 8, a MRAM device may include structuressimilar to those described above with reference to FIGS. 1 to 3,including the integrated circuit substrate 1, the access transistor TA,the bit line 49, and the MTJ 41 therebetween. In addition, a controller89 is coupled to the bit line 49 and the gate electrode 5 of the accesstransistor TA. The controller 89 provides a word line signal to the gateelectrode 5 of the access transistor TA. The access transistor TA isturned on while the word line signal is applied. The controller 89further provides a bit line write signal to the bit line 49 when theword line signal is applied. As a result, the controller 89 can selectthe MRAM cell connected to the gate electrode 5 and the bit line 49, andcan provide a writing current through the bit line 49, through the MTJ41, and through the access transistor TA to provide the functionalitydescribed above with reference to FIGS. 1 to 3. The controller may alsobe coupled to the pair of magnets 52 adjacent opposing sidewalls of theMTJ 41 to provide a current thereto, for example, when the magnets 52are electromagnets.

FIG. 9 is a perspective view of an MRAM device including a controllerconnected thereto in accordance with further embodiments of the presentinvention. Referring to FIG. 9, a MRAM device may include structuressimilar to those described above with reference to FIGS. 4 and 5,including the integrated circuit substrate 1, the access transistor TA,the bit line 491 and the MTJ 41 therebetween. In addition, a controller89 is coupled to the bit line 49 and the gate electrode of the accesstransistor TA. The controller 89 provides a word line signal to the gateelectrode of the access transistor TA. The access transistor TA isturned on while the word line signal is applied by the controller 89.The controller 89 further provides a bit line write signal to the bitline 49 when the word line signal is applied. As a result, thecontroller 89 can select the MRAM cell connected to the gate electrodeand the bit line 49, and can provide a writing current through the bitline 49, through the MTJ 41, and through the access transistor TA toprovide the functionality described above with reference to FIGS. 4 and5. The controller may also be coupled to the magnetic layer 59 onopposing sidewalls and the upper surface of the bit line 49 to provide acurrent thereto, for example, when the magnetic layer 59 is anelectromagnet.

FIG. 10 is a perspective view of an MRAM device including a controllerconnected thereto in accordance with still further embodiments of thepresent invention. Referring to FIG. 1O, a MRAM device may includestructures similar to those described above with reference to FIGS. 6and 7, including the integrated circuit substrate 1, the accesstransistor TA, the bit line 49, and the MTJ 41 therebetween. Inaddition, a controller 89 is coupled to the bit line 49 and the gateelectrode of the access transistor TA. The controller 89 provides a wordline signal to the gate electrode of the access transistor TA. Theaccess transistor TA is turned on while the word line signal is appliedby the controller 89. The controller 89 further provides a bit linewrite signal to the bit line 49 when the word line signal is applied. Asa result, the controller 89 can select the MRAM cell connected to thegate electrode and the bit line 49, and can provide a writing currentthrough the bit line 49, through the MTJ 41, and through the accesstransistor TA to provide the functionality described above withreference to FIGS. 6 and 7. The controller may also be coupled to thepair of magnets 52 adjacent opposing sidewalls of the MTJ 41 and/or tothe magnetic layer 59 on opposing sidewalls and the upper surface of thebit line 49 to provide a current thereto, for example, when the pair ofmagnets 52 and/or the magnetic layer 59 are electromagnets.

According to some embodiments of the present invention as describedabove, a hard axis magnetic field may be provided through a MTJ of aselected MRAM cell concurrently with a writing current applied to theMTJ, in order to selectively switch the magnetization (and thereby alterthe resistance) of the MRAM cell using a spin injection mechanism. Thehard axis magnetic field may be generated by at least one pair ofmagnets adjacent to opposing sidewalls of the MTJ and/or a magneticlayer covering opposing sidewalls and a surface therebetween of the bitline. Accordingly, the write current required to switch the selectedMRAM cell may be reduced with the aid of the hard axis magnetic field.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present invention as defined by the following claims.

1. A magnetic random access memory device comprising: a memory cellaccess transistor on a substrate; a bit line spaced apart from thesubstrate; a magnetic tunnel junction structure electrically coupledbetween the bit line and the memory cell access transistor; and at leastone magnet adjacent a sidewall of the magnetic tunnel junction structureand configured to provide a magnetic field through the magnetic tunneljunction structure.
 2. The device of claim 1, wherein a distance betweenthe bit line and the substrate is greater than a distance between the atleast one magnet and the substrate.
 3. The device of claim 1, whereinthe at least one magnet is configured to provide the magnetic fieldalong a hard magnetization axis of the magnetic tunnel junctionstructure.
 4. The device of claim 1, wherein the at least one magnetcomprises a pair of magnets adjacent opposing sidewalls of the magnetictunnel junction structure at opposite sides of the bit line.
 5. Thedevice of claim 1, further comprising: a controller coupled to thememory cell access transistor the bit line, and the magnetic fieldconductive line, wherein the controller is configured to provide awriting current through the bit line through the magnetic tunneljunction structure and through the memory cell access transistor whilethe at least one magnet provides the magnetic field through the magnetictunnel junction structure.
 6. The device of claim 5, wherein thecontroller is configured to provide a first writing current in a firstdirection to reduce a resistance of the magnetic tunnel junctionstructure and configured to provide a second write current in a seconddirection opposite the first direction to increase the resistance of themagnetic tunnel junction structure.
 7. The device of claim 5, whereinthe controller is further configured to provide a read current that isless than the writing current through the bit line, through the magnetictunnel junction structure and through the memory cell access transistor,and wherein the controller is configured to determine a program statusof the magnetic tunnel junction structure based on the read current. 8.The device of claim 1, wherein the magnetic tunnel junction structureincludes a pinned layer, a free layer, and an insulating layertherebetween, and wherein the at least one magnet is configured toprovide the magnetic field through the free layer of the magnetic tunneljunction structure.
 9. The device of claim 8, wherein the free layer andthe pinned layer comprise a same material.
 10. The device of claim 8,wherein at least one of the pinned layer and/or the free layer comprisesa synthetic anti-ferromagnetic layer.
 11. The device of claim 1, whereinthe at least one magnet comprises at least one permanent magnet.
 12. Thedevice of claim 1, wherein the at least one magnet comprises at leastone electromagnet.
 11. The device of claim 1, wherein the at least onemagnet comprises a first magnet configured to provide a first magneticfield through the magnetic tunnel junction structure, and furthercomprising: a second magnet on opposing sidewalls of the bit line and asurface therebetween opposite the magnetic tunnel junction structure andconfigured to provide a second magnetic field through the magnetictunnel junction structure along a same direction as the first magneticfield.
 14. A magnetic random access memory device comprising: a memorycell access transistor on a substrate; a bit line spaced apart from thesubstrate; a magnetic tunnel junction structure electrically coupledbetween the bit line and the memory cell access transistor; and a magneton opposing sidewalls of the bit line and a surface therebetweenopposite the magnetic tunnel junction structure and configured toprovide a magnetic field through the magnetic tunnel junction structure.15. The device of claim 14, wherein the magnet is configured to providethe magnetic field along a hard magnetization axis of the magnetictunnel junction structure.
 16. The device of claim 14, farthercomprising: a controller coupled to the memory cell access transistor,the bit line, and the magnetic field conductive line, wherein thecontroller is configured to provide a writing current through the bitline, through the magnetic tunnel junction structure and through thememory cell access transistor while the magnet provides the magneticfield through the magnetic tunnel junction structure.
 17. The device ofclaim 16, wherein the controller is configured to provide a firstwriting current in a first direction to reduce a resistance of themagnetic tunnel junction structure and configured to provide a secondwrite current in a second direction opposite the first direction toincrease the resistance of the magnetic tunnel junction structure. 18.The device of claim 16, wherein the controller is further configured toprovide a read current that is less than the writing current through thebit line, through the magnetic tunnel junction structure and through thememory cell access transistor, and wherein the controller is configuredto determine a program status of the magnetic tunnel junction structurebased on the read current. 19.-22. (canceled)
 23. The device of claim14, wherein the magnet comprises a first magnet configured to provide afirst magnetic field through the magnetic tunnel junction structure, andfurther comprising: a pair of second magnets adjacent opposing sidewallsof the magnetic tunnel junction structure and configured to provide asecond magnetic field through the magnetic tunnel junction structurealong a same direction as the first magnetic field. 24.-26. (canceled)27. A method of operating a magnetic random access memory deviceincluding a memory cell having a magnetic tunnel junction structureconnected between a bit line and a memory cell access transistor on asubstrate, and including a magnet on opposing sidewalls of the bit lineand a surface therebetween opposite the magnetic tunnel junctionstructure, the method comprising: providing a magnetic field through themagnetic tunnel junction structure using the magnet; and providing awriting current through the bit line, through the magnetic tunneljunction structure and through the memory cell access transistor whileproviding the magnetic field. 28.-29. (canceled)